Full report

Original page 1

General Disclaimer One or more of the Following Statements may affect this Document This document has been reproduced from the best copy furnished by the organizational source. It is being released in the interest of making available as much information as possible. This document may contain data, which exceeds the sheet parameters. It was furnished in this condition by the organizational source and is the best copy available. This document may contain tone-on-tone or color graphs, charts and/or pictures, which have been reproduced in black and white. This document is paginated as submitted by the original source. Portions of this document are not fully legible due to the historical nature of some of the material. However, it is the best reproduction available from the original submission. Produced by the NASA Center for Aerospace Information (CASI)

Original page 2

TECHNICAL ADVISEMENT MEMORANDUM NO. 171-1 A SURVEY OF SPACEBORNE COMPUTERS PRC D-1237 27 June 1966 GPO PRICE CFSTI PRICE(S) . Hard Copy (HQ Micr©fiche tM1=1 Prepared by n 653 .wh 85 .1^IE-., T,: George Liviakis Approved y Sidn y . Fir s tman PLANNING RESEARCH CORPORATION LOS ANGELES. CALIF. N66 34705 UIOGEff10N NU ) 0 } lip T78S 5 tI ASA OR OR TMX OR AD NUMBER) WASHINGTON, D. C. lTI1RU1 (t:D ID tOATEOORY)

Original page 3

TECHNICAL ADVISEMENT MEMORANDUM NO. 171-1 A SURVEY OF SPACEBORNE COMPUTERS 1. Introduction The purpose of this memorandum is to present the results of a preliminary survey of a set of digital computers generally applicable to the Airborne Evaluation Equipment problem. No attempt was made to draw any conclusions from the data or to select one or more machines over the others. The primary use to be made of these data is the conceptual design of alternate AEE hardware systems. The machines were characterized by numerous parameters, including: 1. Main memory characteristics 2. Scratch pad memory characteristics 3. Arithmetic unit characteristics 4. Addressing structure S. Input/output organization 6. Interrupt system 7. Physical characteristics 8. Operating and environmental characteristics In addition to the fairly standard parameters listed above, others have been introduced that should make the selection more meaningful in terms -of the computer's impact on_ the -overall system or should make comparisons between machines more objective. The added Para- Meters are as follows: 1. Availability of acceptable peripheral devices 2. Compatibility with ground-based computer 3. Maturity and availability of hardware 4. Performance measure It should be understood that this discussion in no way limits the consideration of alternate best system philosophies. The test system may be mechanized with a single centralized computer or with a number of machines distributed among the various vehicle stages. Furthermore, the fact that this document discusses only general-purpose machines should not be taken to imply that special-purpose mechanizations would not be acceptable. 1

Original page 4

This initial look at the Airborne/Spaceborne computer market indicated that there was a wide variety and large number of candidate machines available. This evaluation has been restricted to those computers that weig 100 pounds or less and utilize 300 watts or less due to the restraints of the space environment. However, even these numbers are considered to be in excess of what are felt to be reasonable design goals, and were chosen so as to prevent us froin ignoring highly desirable machines with marginal physical characteristics. 2. Evaluation Parameters Before presenting the data on the machines, it would be well to discuss some of the evaluation parameters, so as to provide the reader with a better understanding of their meaning. In addition, a short discussion of input/output organization will clarify some of the nomenclature used on the data sheets. a. Performance Measure In order to determine whether or not a given machine can perform a specified function or to compare one machine with another, it is necessary to have an unbiased measure of machine performance. Performance is generally considered to be a function of the speed with which a machine can perform a given task and, as such, is greatly dependent on the task selected. To eliminate problems involved in task selection and to make an evaluation of machine speed more meaningful than a simple comparison of add times and multiply times, it was decided to evaluate machine performance based on the relative frequency of instruction use for typical checkout problems. For this purpose, the Eason-Lane mix, developed at the Douglas Aircraft Company, is used. This mix is a variation of the standard Gibson mix and is oriented toward automatic checkout problems. This mix is shown at the top of the following page. 2

Original page 5

Operation Relative Frequency (1) Load, Add, Subtract (indexed) 0.45 (2) Store (indirect) (3) Multiply (4) Divide (5) Branch (6) Logical (7) Shift (6 bits) 0.11 0.02 0.01 0.12 0.19 0.10 The "rated speed" of any machine, with respect to the problems of automatic checkout, is determined using the several operation times weighted by their relative frequencies. b. Compatibility A significant requirement in the selection of any spaceborne computer is the availability of a ground-based machine with a compatible instruction set to be used for support purposes. Manufacturers will normally indicate one or more machines that are directly compatible, having either the same instruction repertoire or a subset that will satisfy the requirement. Alternatively, manufacturers may choose to provide software for such machines as the IBM 7094 or CDC 3600 to functionally simulate the spaceborne computer. The completeness of each simulation package must be considered carefully to ensure that the simulation software will operate under control of existing support computer executive and monitor systems, and that the necessary programming debugging aids are provided. These compatibility factors are noted. C. Input/Output Organization A number of classifying I/O features are included for each machine profile. Most spaceborne machine I/O organizations are tailored to specific applications. It is not uncommon, therefore, to find machines in this class with multistructured I/O centers for processing serial., discrete, or parallel digital data. The I/O interface may even provide for the exchange of analog signals. Most manufacturers will offer a machine interface custom-designed to the user's application. 3

Original page 6

An attempt has been made in this study to ignore these "special I/O Axtures" and to examine the I/O design in terms of basic data path organization and word length. Most of the I/O data word lengths correspond to the C. P. U. word length; however, some machines provide for half-word and character communication modes. Only one manufacturer in th:a survey included parity in the I/O data channel as a standard feature; however, most offer it as an optional feature. The I/O control orgaization is delineated in each machine profile by including the definitio:iz of I/O data path and location of I/O control word(s). To reduce hardware, some machines will utilize the arithmetic unit (i. e. , accumulator' or instruction register) to perform I/O control, whi,.e other, more elaborate machines will provide special registers to hold the current storage address and block length count information. Another useful I/O feature is the ability to access memory by specifying the data address from an external source (e, g. , ESA and ESI as used in UNIVAC machines). This feature provides for very efficient data exchange in certain applications. The maximum data block length that can be directly accessed with one set of I/O control words may vary from a single word to the entire memory. A flexible approach for controlling a continuous series of data transmissions involves the concept of data chaining. Data chaining provides for accessing a number of contiguous or noncontiguous memory buffer regions without program intervention. The ability to chain data, and the extent thereof, is indicated in each profile. In the survey, consideration is given to the number of available interrupt levels and the organization of the interrupt system. No attempt is made to define the individual machine interrupt reaction times or overheads. However, such characteristics as hardware "nesting" of interrupts, the ability to "lock out" interrupts programmably, and the ability to perform dynamic priority reallocation have been indicated in each machine profile. 4

Original page 7

1. Computer Data Sheets The following pages contain data sheets for all computers evaluated to'date and a summary chart of all major characteristics. The computer survey is not yet complete as there are a :ew machines on which manufacturer's data have not yet been received. 7 5

Original page 8

Con-iputer. IBIv[-4ir (T P a) MAIN MEMORY: word length: 32 Pits + 4 parity cycle time: 2. 5 μ sec. capacity: 165 K words parity check: yes protection: software memory protect type: core b) SCRATCH PAD M) MORY: word l cligth: none cycle time: none capacity: none parity: none type: none c) ARITHMETIC FEATURES: f) PHYSICAL CHARACTERISTICS 8K MEM 16K MEM 32.1K )\ EON weight: 52 lbs 63 lbs 85 lbs volume: . 84 cu. ft. 1. 09 cit. ft. 1. 60 cu. 1 power: 300 watts 380 watts 540 watts] implcrr,cntation: I. C. (T. T. L) g) OPERATINC'T CHARACTERISTICS: MTBF: 5000 lhrs (for lab. enviro»ment) temp: ) vibration: ) MIL-E-5400 h) PERTPIIERAL DEVICES: bull: storage: Druir,., CRT: - typewriter: - data representation: binary, 2s comp. others: Mag, tape unit serial/parallel: parallel no. of registers(G. P. ): 16 h^Lrdware ratinber of hist.: 129 (78 basic) instruction word: 32 hits op. code field: 8 bits i) COMPATIBILITY: Directly coinpatible upward on all II3M 360 models (front model 40) aciclrc^ss field; ?.4 bits Inter-i-ecrister add time: 5. 01 μ sec. 1. 66 u sec. multiply time: 10. 08 p sec. 8. 75 u sec. d) ADDRESSING: index registers: 16 G. P. hardware indirect: no e`fective address: All memory can be directly addressed relative to base registers access to general loc: direct, indexed, branch and lint; e) INPU'.r/O'JTPUT: channels: 3 including mux,selector, and direct data l end the 8 bit parity: memory-channel buffer basic I/O data path: tiA j) EQUIPMENT MATURITY: flight proven 'zardwarc availability: early 1967 k) OTHER FEATURES: 1) micro program - is alterable L) SOFTWARE.: Assembler Service routines Compiler word rate: mux. mode: 33K bytes/sec. ; burst mode: 160K bytes/scc. 1/0 control ,word loc.: I/O channel hardware max. block length: 6-1, 000 bytes chaining: automatic chain of variable field lengths ir_ter.-upt levels: 16 nestint : yes d}na mic priority assigninent: v- -s ". DRUM SPECS. Storage: 10 6 bits Speed: 1.2000 RPN/l Wt: 2. 5 lbs. VOIL'nle: 40 cu. iii. Power: 20 watts

Original page 9

a) MAIN MEMORY: word length: 16 bits (32 bit optional) cycle time: 2. 5 4 sec. capacity: 32K words parity check: yes protection: software memory protect type: core b) SCRATCH.PAD MEMORY: word length: none cycle time: none capacity: none parity: none type: none c) ARITHMETIC FEATURES: data representation: binary, 2s comp. serial/parallel: parallel no, of registers (G. P : up to 8 360 set 1800 sPt no. of inst: 129 (51 basic) 31 instruction word: 32 bits 32 bits op. code field: 8 bits 5 bits address field: 16 bits 16 bits add time: 8. 50 p sec. 5 μ sec. multiply time: 41. 5 μ sec, 12.p sec. d) ADDRESSING: f) PHYSICAL CHARACTERISTICS: 8K mem weight: 37 lbs. volume: .8 cu. ft. power: 250 watts implementation: IC. (TTL) g) OPERATING CHARACTERISTICS: MTBF: 3000 hrs. temp, -.% MIL-E- 5400 vibration: S h) PERIPHERAL (SPACEBORNE) DEVICES: bulk storage: Drum* CRT: - NA typewriter: - NA others: Mag. tape i) COMPATIBILITY: 1800 set option: Directly compatible IBI4 1800 simulator available for 7090-94 3_.60 set option: Directly compatible upward IBM 360-40 j) EQUIPMENT MATURITY: flight proven hardware available early 1967 index registers: 8 located in memory k) OTHER FEATURES: indirect: no effective address: All memory can be addressed relative to base registers 1. Optional instruction set. access to general loc.: direct, indexed, L) SOFTWARE: branch and link 4e) INPUT/OUTPUT: channels: 2 including mux and direct data length: 8 bit parity: yes basic I/O data path: memory-channel buffer word rate: mux mode: 33K bytes /sec; burst mode 160 K bytes/sec I/O control word loc: I/O channel hardware max. block length: 64000 bytes chaining: yes - variable field lengths interrupt levels: 8 nesting: yes dynamicc priority assignment: yes Assemblers Service Programs Compilers Simulator (for 1800 opt. j DRUM: 166 bits capacity 12000 RPM 2. 5 lbs. 40 cu. in. 20 watts

Original page 10

Computer: AUTONETICS-D26C a) MAIN MEMORY: word length: 30 Bits cycle time: 6 ti Sec. capacity: 8-32 K Words parity check: None protection: Power Protection type: Core b) SCRATCH PAD MEMORY: word length: 30 Bits cycle time: 1 p Sec. capacity: 256 Words parity: None type: Core c) ARITHMETIC FEATURES: data representation: Binary, 2C serial/parallel: Parallel number of registers (.G.P): - NA number of inst: 87 instruction word: 3'0 Bits op. code field: 7 Bits address field: 14 Bits add time: * 6-12uSec . multiply tire: 33-45 μSec. d) ADDRESSING: index registers: 1 Hardware.6 MEM (scratch pad) indirect: No effective address: Direct f) PHYSICAL CHARACTERISTICS: 8 KMemr^r 32K Memory weight: 7 lobs.68 IF volume: .65 cu. ft. .85 cu. ft. power: 175 watts 220 watts implementation: I. C. g) OPERATING CHARACTERISTICS: MTBF: 15,600 hrs.' temp.: -40 oC to + 65 oC vibration: 20g RMS at 10 - 20 KCPS h) PERIPHERAL DEVICES: bulk storage: Disk available CRT: - NA typewriter: - NA others: - NA i) COMPATIBILITY A simulator program for the IBM 7094 permits use of this machine to checkout D • 26C Prog. j) EQUIPMENT MATURIT f Flight tested in Nor... American T-39 airplane k) OTHER FEATURES: 1) Real time clock access to general loc.: Direct, Index, 2.) ESA Return Jump 3) Three special purpose I/O processc e) INPUT/OUTPUT : channels: ** One input, one output data length: Character of word parity: No L) SOFTWARE: 1) Simulator (IBM 7094) 2) Assembler (IBM 7094 fap), . 3) Compiler basic I/O data path: MEM - 1/0 Channel 4) Utility word rate: 13, 800 words / sec or 33, 000 CHAR/Sec.' I/O control word loc: Scratch pad memory max. block length: 32K chaining No interrupt levels: 8 nesting: no dynamic priority assignment: No, Programmed ENABLE /.'DISABLE * Add time dependent on location bf oper and in main and scratch pad memory '_* Three separate -I/0 processors provide for parallel, analog, or discrete data exchange

Original page 11

f a) MAIN MEMORY: f) PHYSICAL CHARACTERISTICS: r(inc u e s P. . and MEM) • word length: 12 or 16 Bit (Optional) cycle time: 6 L4 Sec. capacity: 1K - 16K words parity check: none protection: Transient type: Core F ) OPERATING C.HARA%jERISTICS: b) SCRATCH PAD MEMORY: word length: none cycle time: none capacity: none weight: 20 lbs volume: .21 cu. ft. power: 6L watts implementation: Int egrated CKT (DTL) MTBF: 18, 00t, hrs. temp.: -40 `'C. to + 65" C. vibration: 20g RMS 10-2000 CPS. parity: none h) PERIPHERAL DEVICES: type: none c) ARITHMETIC FEATURES: data representat,.on: Binary, 2's complement bulk storage: • Disk storage (1096-12K CRT: NA 'words) 5MS avg. access time typewriter: - NA others: - NA serial/parallel: Parallel i) COMPATIBILITY: number of registers (G. P. ): 1 number of inst: 27 Software simulation pkg. available instruction word: 12 or 16 Bit (Optional) to enable chedout of programs on the op. code field: 5 Bits address field: 7 or 9 Bits add tirne: 12 m Sec. j) multiply time: 42 ,<t Sec at 12 Bits 54,N Sec at 16 Bits d) ADDRESSING: k) OTHER FEATURES index registers: None indirect: None IBM 7094 or CDC 3610. EQUIPMENT MATURITY- Flight tested at Holloman AFB on F106 and C130. NA effective address: relative to bank L) SOFTWARE: register address access to general loc.: direct, return simulator package jump. e) INPUT/OUTPUT: channels: single bilateral data length: 12 or In Bit (optional) parity: none basic I/O data path: Memory-arithmetic unit - I/O chann-4 word rate: 13, 800 words/sec. max serial processor, 138, 000 word/sec parallel - I/O control word loc.: instruction register max. block length: 1 word chaining. none processor (optional mechanization) interrupt levels: One, designed into 1/0 hardware nesting: none dynamic priority assignment- done I/O is tailored to need: the basic unit contains A-D, D-A and oth-r signal conditioning hardware to provide exchange of discrete and analog data

Original page 12

Computer: NORTHROP NDC-1051 a) MAIN MEMORY: word length: 24 Bits cycle time: 2,u Sec. capacity: 2-8K words parity check: No protection: Yes - power transient type: Core b) SCRATCH PAD MEMORY: word length: none cycle time: none capacity: none parity: none type: none c) ARITHMETIC FEATURES: data representation: Binary 2's comp. serial/parallel: Parallel number of registers (G. P. ): 1 number of inst: 39 instruction word: 24 Bits op. code field: 6 Bits address field: 12 Bits add time: 8," sec. multiply time: 72 ,u Sec. d) ADDRESSING: f) PHYSICAL CHARACTERISTICS: K memory) weight: 28.6 lbs. volume: .5 cu. ft. power: 140 watts implementation: integrated CKT. g) OPERATING CHARACTERISTICS MTBF: 8500 hrs. temp.:) MIL-F-5400G vibration: j h) PERIPHERAL DEVICES: bulk storage: Disk memory (7 5M Os CRT: - .NA typewriter: - NA others: - NA i) COMPATIBILITY: Not compatible with any machine, no simulater written j) EQUIPMENT MATURITY: Two prototypes developed - to be tested on inertial platform in-house index registers: 7 located in memory k) OTHER FEATURES: indirect: yes -effective address: Direct to 4K words indexed access to general loc: eittend to additional 4K by bank sei :t command; all addressing relative to roll arrow; return jump. e) INPUT/OUTPUT: L) SOFTWARE _- Charnels: One buffered I/O controlled ext. or by program data length: 24 bits parity: None - can be added opt. basic 1/0 data path: memory-arith unit - I /0 channel word rate: 250 K words max. I/O control word loc.: accumulator max. block length: one word chaining: none Interrupt levels: none with basic machine, can be added optionally Nesting: none Dynamic priority assignment: none

Original page 13

Computer: HONEYWELL - ALERT a) MAIN MEMORY: word length: 24 Bits cycle time: 1 p Sec. Read, 4,U Sec. Write capacity: 4-32K words parity check: none protection: power failureprotect type: Micro Biax or Core D. R. O. b) SCRATCH PAD MEMORY: word length: none cycle time: none capacity: none parity: none type: none c) ARITHMETIC FEATURES: data representation: Binary serial/parallel: Parallel number of registers (G. P. ): 1 number of inst: 64 instruction word. 24 bits op. code field: 6 Bits address field: 15 Bits add time: 2. 0 m sec. multiply time: 12.0 , u Sec. d) ADDRESSING: index registers: Six hardware indirect: yes, multi-level f) PHYSICAL CHARACTERISTICS: (8K MEM) (16K MEM) weight: 60lbs 86 lbs. volume: 1. 21 cu. ft. 1. 57 cu, ft. power: 194 watts 274 watts implementation: integrated CKTS-TTL. g) OPERATING CHARACTERISTICS: MTBF: 10, 000 hrs. temp.: -53 oC. to + 85 oC. vibration: t lOg at 70-500 CPS. h) PERIPHERAL DEVICES: bulk storage: Tape unit CRT: - NA typewriter: - NA others: - NA i) COMPATIBILITY: Honeywell 800 j) EQUIPMENT MATURITY: Qualification testing k) OTHER FEATURES: 1. Character or word effective address: Direct to 32K words addressing access `o general loc.: Direct, indirect,, 2. Self test fixtures indexed e) INPUT/OUTPUT: Channels: One direct channel, up to three buffered channels L) SOFTWARE H-800 simulator Assembly Prog (SHAP-8) Data Length:6 or 24 Bits-Buffered channel, discretes - direct channel Parity: none Basic 1/0 data path: memory- I/O buffer register Word rate: Buffered: 166Kwords/sec. ; Direct: 70 K words/sec. 1/0 control word loc.: Buffered: I/O channel register inax: block length: 512 words chaixing: No. - but can automatically repeat block Interrupt levels: 8 exte.rnal, expandable to 24 levels Nesting: Yes. Dynamic priority assignment: yes

Original page 14

Compu ter: CO NTR OL_, DATA - 5400-8 a) MAIN MEMORY: word length: 24 bits cycle time: 3. 0 U sec. capacity: 32, 256 words parity check: no protection: Yes - power transient type: core b) SCRATCH PAD IVE MORY: word length: 24 bits cycle time: Z. 5usec.. capacity: 2048 words parity: no type: core c) ARITHMETIC FEATURES: f) PHYSICAL CHARACTERISTICS: 16 K 8K weight: 70 lbs. 46 lbs. volume: .851 cu. ft. power: 230 watts implementaton: integrated ckts. g) OPERATING CHARACTERISTICS: MTBF: 4750 firs. temp.: NA vibration: NA h) PERIPI_IERAL DEVICES: bulk storage: none CRT: none typewriter: none others: none data representation: Binary, 2 s complement serial /parallel: parallel number of registers (G. P. ): 2 nun-iber of inst: 64 instruction words: 24 bits op. c ode field: 6 bits address field: 15 bits add time: 6 u sec. multiply time: 18. 0 u sec. (12 bits) 30. 0 μ sec. (24 bits) d) ADDRESSING: index registers: 4 Hardware indirect: Yes effective address: Direct to 32K words access to general loc. : index, direct, indirect e) INPUT/OUTPUT i) COMPATIBILITY: CDC 1604, CDC 3600 ,Simulltion soft,,vare can assemble program on these machines J) EQUIPMENT MATURITY: components fli ght tested k) OTHER FEATURES: 1) Program "loot.-ahead t 2) Real Time Clock 3) Ext. I/O controlled addressing L) SOFTWARE,: See: 5400 Profile channels: one ext controlled I/O channel, one prog. controlled I/O channel data length: 24 bits parity: none basic I/O data path: Ext. controlled: Memory- I/0; prop. control led:memory—;S--;X I/0; Data --^ X Adder-) AC G> Memory word rate: 333 'k-c. Ext. Contr olled; progr. controlled: 83 kc I/O control word loc.: Ext. controlled: by ext. device; prop control: 1`IA max. block length: 512 chaining: no interrupt levels: 3- type 1; 16 type 3(ext. ) nest.;n g : ves dynamic priority assignment: no - has mask register to disable interrupt

Original page 15

Computer: CDC 5400 a) MAIN MEMORY: (Instructions) word length: 24 Bits cycle time: 2. 5 μ sec. capacity: 32K words parity check: no protection: yes - power transient type: thin film NDRO b) SCRATCH PAD MEMORY: (Variables) word length: 24 bits cycle time: 2. 5 μ sec. cz.pacity: 4K words parity: no type: core DRO c) ARITHMETIC FEATU.".ES: data representation: binary, 2C serial/parallel: parallel number of registers (G. P): 2 number of inst. 70 instruction. word: 24 bits op. code field: 6 bits address field: 15 bits add time: 2. 5 - 3.•1 u sec. multiply time: 15. Op sec. at 12 I-its 24. 0 u sec. at 24 bits d) ADDRESSING: index registers: 4 hardware indirect: yes effective address: direct to 32K access to general loc.: indexed, direct,indirect e) INPUT/OUTPU T f) PHYSICAL CHARACTERISTICS: 16K 8K weight: 45 lbs volume: 1.1 cu. ft. . 55 cu. ft. power: 190 watts implementation: integrated DTL g) OPERATING CHARACTERISTICS MTBF: 4750 jars. vibration: ) MIL-E-5400 h) PERIPHERAL DEVIC ES: bulk storage: No airborne peripherals CRT: No airborne peripherals typewriter: No airborne peripherals other: No airborne peripherals i) COMPATIBILITY: Simulator software permits program assembly in either CDC 1604 or 3600 i j) EQUIPMENT MATURITY: Components flight tested k) OTHER FEATURES: 1) Real time clocl 2) Look ahead 3) Externally sp.: fied addressing L) SOFTWARE: 1) Assembly System 2) Simulator 3) Utility channels: 3 (external, prog,andspecial 4) Debugging aids controlled) data length: 24 bits parity: none basic I/O data path: Programmed: Input: Data -.^ X -4 Adders Acc _.a Mem Output: memory OCU --,^ S —+ X-aData Ext: Memory - I/O channel word rate: Prog: 100K words/sec; Ext: 400 K words/sec. ; special: 100 K words/sec I/O control word loc: Prog.: memory, ext: via ext device max. block length: 512 chaining: no interrupt levels: 16 external nesting: yes dynamic priority assignment: no -pro; enable/disable of interrupts only

Original page 16

Computer: CDC-5360 a) MAIN M MORY: word length: 24 Bits cycle time: 6 μ Sec. capacity: 8K - 32K parity check: No protection: Yes - Power Transient type: Core b) SCRATCH PAD MEMORY: word length: None cycle time: None capacity: None parity: None type: None c) ARITHMETIC FEATURES: f) PHYSICAL CHARACTERISTICS: 8 K Mem. weight: 35 lbs. volume: . 6 cu. ft. power: 125 Watts implementation: Integrated CKT. g) OPERATING CHARACTERISTICS MTBF: 2840 hrs. temp.: ) MIL-E-5400 vibration:) h) PERIPHERAL DEVICES: bulk storage: No airborne peripherals CRT: No airborne peripherals typewriter: No airborne peripherals others: No airborne peripherals data representation: Binary, 2,s Complement serial/parallel: Parallel no. of registers (G. P. 2 number of inst: 31 instruction word: 24 Bits op. code field: 5 Bits address field: 15 Bits add time: 12 p Secs multiply time: 90 p Sec. d) ADDRESSING: index registers: 28 located in core indirect: yes i) COMPATIBILITY: Assembly language (MICAP) operated on CDC 1604, CDC 3600 prepares object code for 5360. via simulation package. j) EQUIPMENT MATURITY: Fire control calculations for Hughes PHOENIX air-air missile k) OTHER FEATURES: effective address: directly addressable to 5Z K. access to general loc.: Direct, indexed, Optional: external specified address Indirect e) INPUT/OUTPUT L) SOFTWARE channels: 2-24 Bit parallel I/O channels; Assembly program 2-8 Bit parallel I ./0 channels; 2-serial utility input, (1 serial);also: 24 discrete inputs diagnostic (8 are output channel interrupts) data length: 24 Bit, 8 Bit, serial bus parity: None simulation basic 1/0 data path: memory.;—^ acctunulator I/O channel word rate: 18, 300 words/sec, 83, 500 words/sec (short), 167, 600 bits/sec. serial I/O control word loc.: arithmetic unit max. block length: 1 chaining: no f ' interrupt levels: 8 nesting: no dynamic priority assignment: No

Original page 17

Computer:- HUGHES HCM-206 I a) MAIN MEMOR f: word length: 32 Bits cycle time: 2 μ Sec. capacity: 8-32K parity check: Opt:. protection: Power transient type: Core I b) SCRATCH PAD MEMORY: (Optional) word length: Part of main mem. cycle time: can be wired to capacity: operate scratchpad parity: type: c) ARITHMETIC FEATURES: data representation: Binary, 2C serial/parallel: Parallel number of registers (G. P. ): 8- Hardware number of inst: 64 instruction word: 16 and 32 Bits op. code field: 6 Bits address field: 16 Bits add time: 2 μ Sec. multiply time: ) Sec at 16 Bits 15uSec at 32 Bits d) ADDRESSING: index registers: * 8 hardware indirect: yes effective address: Direct to 32 K words access to genera: loc: Direct Indirect Indexed Ret. Jump. e) INPUT/OUTPUT f) PHYSICAL CHARACTERISTICS: 8K Mem. weight: 20 lbs. volume: .375 cu. ft. power: 250 watts implementation: I. C. (DTI,) bl OPERATING CHARACTERISTICS: MTBF: 6,400 brs.. temp.: -54 0C to +850C vibration: 10 cps.RMS at 1KC. BW. h) PERIPHERAL DEVICES: bulk storage: Drum (See NCM 205profile CRT: NA typewriter: others: i) COMPATIBILITY: Simulator for IBM 7094 j) EQUIPMENT MATURITY: Prototype in development phase k) OTHER FEATURES: 1) flo;.:ting point hardware 2) Scratch pad option 3) Memory bani:s, independent access L) SOFTWARE: (Available 2 67) 1) Simulator 2) Assembler 3) Compiler 4) Monitor 5) Library 6) Diagnostics channels: Two (one to each indep. mem. bank) data length: 32 Bits parity: No basic 1/0 data path: Mem- I/0 -hannel word rate: 500 K words/sec/mem. bank 1/0 control word loc.: 1/0 channel hardware max. block length: 32K. chaining: no interrupt levels: 32 nesting: yes dynamic priority assignment: Yes *Index registers are 32 bits including both address and countdown fields.

Original page 18

W. Computer: H UGHE'S NG M- 205 a) MAIN MEMORY: word length: 18 Bits cycle time: 2 u sec. capacity: 2-8K parity check: no protection: Power transient type: Core DRO b) SCRATCH PAD MEMORY: (optional) word length: Part of main memory cycle time: canbc wired to operate capacity: s c ratchpad. parity: type: c) ARITHMETIC FEATURES: data rep resentation: Binary, 2C serial/parallel: Parall.el number of registers (G. P): - NA number of inst: 42 instruction word: 18 Bits op code field: 5 Bits address field: 10 bits add time: 4 U Sec. multiply tixn:.: 24 U Sec. d) ADDRESSING: index registers: 3 Fardware indirect: yes effective address: Direct 1K Banka.nd f) PHYSICAL CHARACTERISTICS: 8K memory_ weight: lambs volum e: . 2 cu. ft. powe r: 110 watts Implementation: I. C. (ITL.) g) CiPERA11 NG CIIARAC`I'E RISTICS: MTBF: 15,000 hrs. Temp: - 54 0 to +85 oC Vibration: 10 g's RMS at 1.000 CPS BU' h) PERIPI3ERAL DEVICES: bulk storage: Drum* CRT: - NA typewriter: - NA others: - NA i) COMPATIBILITY: With. simulator compatible with IBM 7094. Another simulator to be available for GE 600 series j) EQUIPMENT MATURITY: Prototype in evaluation phase k) OTHER FEATURES: 1) Scratch pad option relative to base add reg. access to general loc: Direct, Indirect, Indexed, Ret. Jump. e) INPUT/OUTPUT: Channels: One bilateral data length: 18 Bits parity: No basic I/O data path: M.em to 1/0 channel word rate: 500K words/sec. L) SOFTWARE: (To be ready 8/66) -- 1) As s embi-e r 2) Simulator 3) Diagnostics ^ 4) Library I /0 control word loc.: I/O chin. hardware max. block length: 8 K. chaining: no. Interrupt levels: One Nesting: No Dynamic priority assignment: No. DRUM: Capaci^y: 6. 08110 5 Bits Access: 6 MS. Aver. Access Wt. 7. 5 lbs. Powe r: 75 watts Volume: .138 cu. ft.

Original page 19

a) MAIN MEMORY: word length: 48 bits cycle time: 4 p sec. capacity: 3K-18K words (i. e. 16 bit words) parity check: no protection: software power surge protect type: thin film-NDRO I b) SCRATCH PAD MEMORY: word length: 24 bits cycle time: 4 usec -- capacity: 256 words parit y: no type: core-DRO I c) ARITHMETIC FEATURES: f) PHYSICAL CHARACTERISTICS: max memory config. (18K) weight: 55 lbs. volume:. 67 cu. ft. power : 95 watts implementation: integrated ckt, DTL g) OPERATING CHARACTERISTICS: MTBF: 10, 000 hrs. temp.: MIL. STD-810 vibration: FS - 151A USAF-BSD 62-87 h) PERIPHERAL DEVICES: bulk storage: mag. tape CRT: NA data representation: Binary, 2s complement typewriter: NA serial/parallel: parallel no. of registers (G. P): 1 no. of inst: 45 instruction word: 16 bits op. code field: 5 bits address field: 8 bits add time: 8 μ sec. multiply time: 64 u sec. I d) ADDRESSING: index registers: 3 registers located in thin film memory indirect: no effective address: relative to bank address register others: NA i) COMPATIBILITY: Compatible with UNIVAC 1206, 490 and 1230 with interpreter simulator software package j) EQUIPMENT MATURITY: Airforce Guidance Corlputer Titan III SABRE k) OTHER FEATURES: 1. ESI access to general loc.: direct, indexed, 2. Real time clock return jump e) INPUT/OUTPUT channels: 2 buffered 1/0 (actual config. tailored to requirement) data length: - 24 bits parity: no 3. I/O custom to requirements L) SOF T WARE: Assemblers (1824 and 1206) interpreter for 1206 (service library) basic 'I/0 data path: memory-I/0 Chan. or acc. - I/O channel word rate: Direct: 120, 000 words/sec; indirect: 82, 000 word/sec. I/O control word loc.: accumulator max. block length: 1 ch aining: no interrupt levels: 2 nesting: no dynamic priority assignment: no

Original page 20

Computer: IBM - LVDC a) MAIN MEMORY: word length: 26 bits cycle time: 2psec. capacity: 4,-32K words parity check: yes protection: parity only type: core b) SCRATCH PAD MEMORY: word length: none cycle time: none capacity: none parity: none type: none c) ARITHMETIC FEATURES: data representation: binary, 2s comp. serial/parallel: serial no. of registers (G. P): 1 no. of inst. 18 instruction word: 13 bits op. code field: 4 bits address field: 9 bits add time: 82 p sec. multiply time: 328 p sec. separate add/sub and mul/div arith. units d) ADDRESSING: index registers: none indirect: none effective address: 1) relative to sector * address. 2) direct to a 256 word sector register access to general loc.: direct, hop Sector: 256 words e) INPUT/OUTPUT: channels: one data length: serial bus only parity: no basic I/O data path: via accumulator f) PHYSICAL CHARACTERISTICS: 32K memory (w. o. power supply weight: 78. 5 lbs. volume: 2. 2 cu. ft. power: 142 watts implementation: integrated CKT and delay lines g) OPERATING CHARACTEPISTICS: MTBF: 25, 000 hrs. temp: MIL-E-5400 vibration• h) PERIPHERAL DEVICES: bulk storage: Drum* CRT: - NA typewriter: NA others: mag. tape unit (GEMINI) i) COMPATIBILITY: compatible with IBM 7090--7094 with simulator package j) EQUIPMENT MATURITY: used in SATURN vehicle for navigation. k) OTHER FEATURES: separate mul/div - add/sub arith. unit L) SOFTWARE: assembler word rate: 12, 000 words/sec (156, 000 bits/sec. ) I/O control word loc.: instruction register max. block length: single word chaining: no interrupt levels: one - nesting: no dynamic priority assignment: no DRUM' • 10 6 bits storage 12, 000 RPM 2. 5 lbs. 40 cu. in. 20 watts

Original page 21

Computer: LITTON L -306 a) MAIN MEMORY: word length: 32 bits cycle time: 1. 8 μ sec. capacity: * 131 K words parity check: no protection: power failure type: core b) SCRATCH PAD MEMORY: word length: n ne cycle time: capacity: parity type: c) ARITHMETIC FEATURES: data representation: Binary, 2C serial/parallel: parallel no. of registers: 8 G. P. (memory) no. of inst: 63 instruction word: 32 bits op. code field: 6 bits address field: 16 bits add time: 1. 8 μ sec. multiply time: 8.1 μ sec. d) ADDRESSING: index registers: 8 X64 prog. levels (memory) indirect: yes effective address: Direct to 32K words relative to bank add reg. to 131K access to general loc.: Direct, Indirect, Indexed, Ret. jump e) INPUT/OUTPUT: channels: 8 I/O exchang- -nits data length: 32 bits or 8 bit char. parity: r. o f) PHYSICAL CHARACTERISTICS: 8K me_ mory weight: 46 lbs. volume: .36 cu. ft. power: 140 watts implementation: I. C. (TTL) g) OPERATING CHARACTERISTICS: MTBF:'> 2300 hrs. temp.: -55 0C to + 125°C. vibration: NA h) PERIPHERAL DEVICES: bulk storage: No peripherals CRT: typewriter: others: i) COMPATIBILITY: interpretive simulator permits assembly on IBM 7094 j) EQUIPMENT MATURITY: development phase k) OTHER FEATURES: 1) multiprocessing capability 2) look ahead L) SOFTWARE: 1) Simulator (IBM 7094-94) 2) Assembler 3) Diagnostics 4) Service routines 5) Function subroutines basic I/O data path: Mem. -I/0 exchange channel word rate: 278 K words/sec. or 556K words/sec burst mode I/O control word loc.: memory max. block length: 4K words or 4K characters (8 bit) chaining: no interrupt levels: 64 nesting: yes dynamic priority assignment: No. program interrupt enable/disable only (activation) Note: The L -304 and L-305 are similar to L -306 with exci p t-ion denoted: Add Time Multi-,-,ly Vol. Wt. Power L-304 6. 3 μ sec. 19. 8-34 μ sec. .28 cu. ft. 38 lbs. 100 W. L-305 3. 6 μ sec, 9.9-17 μ sec. . 31 cu, ft. 40 lbs. 120 W. * 4K modules at 1. 6 μ sec. cycle time optional

Original page 22

Computer: LITTON L-3060 a) MAIN MEMORY: word length: 32 bits cycle time: 1.8 4sec. capacity: * 8-131K words parity check: none protection: power failure type: core b) SCRATCH PAD MEMORY: word length: None cycle time: capacity: parity: type: c) ARITHMETIC FEATURES: data representation: Binary, 2c serial /parallel: parallel no. of registers (G. P): 16 (memory) number of inst: 500 inst and variations (64 basic) instruction word: 16 or 32 bits op. code field: 6 bits address field: 16 bits add time: 1. 8 u sec. multiply time: 4. 5 - 8.1 p sec. d) ADDRESSING: index registers: 7 G. P. (memory) i d' ect•n it . yno effective address: direct to 32K words relative to bank add. reg. to 131K access to general loc.: Direct, indirect f) PHYSICAL CHARACTERISTICS: 8K Me m. weight: 50 lbs. volume: .38 cu. ft. po,,s, er: 150 watts implementation: IC. (TTL) g) OPERATING CHARACTERISTICS: MTBF: > 2100 hrs. temp.: -550 C to + 1250C. vibration: NA h) PERIPHERAL DEVICES: bulk storage: no peripherals CRT: typewriter: others: i) COMPATIBILITY: interpretive simulator permits assembly on IBM 7094 j) EQUIPMENT MATURIT Y: development phase k) OTHER FEATURES: 1) multi processor capability L) SOFTWARE: 1) Simulator 2) Assembler indexed, return jump 3) Diagnostics e) INPUT/OUTPUT• channels: up to 8 I/O exchange units data length: 32 bits or 8 bit char. parity: no 4) Service routines 5) Function subroutines basic I/O data path: memory-I/0 exchange word rate: 278 K burst mode I/O control word loc.: memory max. block length: 4K words or 4K char. chaining: no interrupt levels: 64 nesting: Yes dynamic priority assignment: No - program enable/disable 4 K modules at 1. 6 p sec Available Optionally Note: L-3040 and L-30 0 are similar to L-3060 with exceppt^ions noted: Add Mult Wt. Yol. Power L-3040 6-m4 sec. 12. =- . 5 p sec. W, ._28 cu. ft. 110 W. L-3050 3. 6 p sec. 6. 3 - 9. 9 p sec. 44# . 33 cu. ft. 130 W.

Original page 23

Computer: TRW MARCO-4418 a) MAIN MEMORY: word length: 18 bits cycle time: 5 μμ sec. capacity: 2- 8 K words parity check: no protection: no type: core b) SCRATCH PAD MEMORY: Optional word length: trade off with main cycle time: memory to 4K. capacity: parity: type: C) ARITHMETIC FEATURES: data representation: binary serial/parallel: parallel no. of registers (G. P); ,NA no. of inst: 27 instruction word: 18 bits op. code field: 5 bits address field: 12 bits add time: 10 p sec. multiply time: 70 p sec. d) ADDRESSING: index registers: one hardware indirect: no effective address: Direct address to 4K relative bank register to 8K access to general loc: index, direct e) INPUT/OUTPUT: channels: One basic bilateral data length: 18 bits parity: no basic I/O data path: via accumulator word rate: 33, 000 words/sec. I/O control word 10L.: arithmetic unit max. block length: one word chaining: no interrupt levels: one line nesting: none dynamic priority assignment: none I/O includes interface to handle: Discretes Scrial binary Analog Pulse data f) PHYSICAL CHARACTERIS'.wICS: 8K mem. weight: 32.^Ibs. volume: .56 cu. ft. power: 75 watts implementation: integrated ckt. (DTL) g) OPERATING CHARACTERISTICS: MTBF: 20, 000 hrs. temp.: ) to NASA spec. vibration; At h) PERIPHERAL DEVICES: bulk storage: - NA CRT: - NA typewriter: - NA others: -Leach mag. tape i) COMPATJBILITY: Simulated on 7094 and GE 635 j) EQUIPMENT MATURI i'Y: Used in NASA LEM (Lunar exclusion module) k) OTHER FEATURES: NA L) SOF_.I'WARE: 1) assembly program 2) simulator interpretive 3) diagn(:,:,tics 4) service library

Original page 24

Computer: UNIVAC 1830-A a) MAIN MEMORY: word length: 36 bits f) PHYSICAL CHARACTERISTIC S: 32K weight: 190 lbs. cycle time: Z .1. sec (has overlapped mem. ) volume: 3 cu. ft. capacity: 32K up to 131K words parity check: none protection: software-power surge type: core b) SCRATCH PAD MEMORY: (Optional) word length: None with basic unit cycle time: None with basic unit capacity: None with basic unit parity: None with basic unit type: None with basic unit c) ARITHMETIC FEATURES: power: 567 Watts implementation: integrated ckts. g) OPERATING CHARACTERISTICS: MTB.F: 4500 hrs. temp: MIL-E-5400 vibration: i h) PERIPHERAL DEVICES: bulk storage: No spaceborne periph. CRT: typewriter: w others: p data representation: Binary one's complement serial/parallel: Parallel no. of G. P registers: 1 no. of inst: 62 instruction word: 30 bits op. code field: 6 bits address field: 15 bits add time: M 2 μ sec. (assumes overlap) i) COMPATIBILITY: directly compatible withUNIVAC 1230 j) EQUIPMENT MATURITY: multiply * time: 18 p sec. (assumes overlap) equipment in development phase d) ADDRESSING: index registers: 7 hardware indirect: limited to indirect jump effective address: direct, indexed access to general loc.: indexed, k) OTHER FEATURES: 1. ESI or /and ESA L) SOFTWARE: direct, indirect return jump, bank Assembler (AS-1) relative if 232K memory e) INPUT/OUTPUT: channels: 16 I/O channels data length: 30 bits parity: none Compiler (CS-1 Utility Diagnostics Mathematical basic I/O data path: memory - I/O channel word rate: 167, 000 words/sec I/O control word loc.: core max. block length: 32K words chaining: no interrupt levels: 81 nesting: none dynamic priority assignment: no M add 2 u se if overlapped memory is not utilized, (i. e. where instruction and operand are iri different banks)

Original page 25

I MACHINE MAIN MEMORY Cycle Word Time Capacity Overlap Size μ sec) 10 3words Banks I AUTONETIC D26C 30 6 32 AUTONETIC D261 12 6 16 CDC 5360 CDC 5400 CDC 5400 -8 HONEYWELL- ALERT or 16 24 6 32 I 24 2.5 32 24 3.0 32 24 5.0 32 HUGHES HCM205 18 2.0 8 HUGHES HCM206 32 2.0 32 IBM 4n - CP :I3M 4Tr - EP + 16 2.5 32 32 2.5 165 LITTON L-304 32 1.8 131 LITTON L-305 32 1.8 131 Yes LITTON L-306 32 1.8 131 LITTON L-3040 32 1.8 131 LITTON L-3050 32 1.8 131 LITTON L-3060 32 1.8 131 NORTHROP 4 NDC-1051 TRW 4418 24 2.0 8 18 5.0 8 UNIVAC 1824-C 48 4.0 6 UNIVAC 1830-A 30 210 131 Yes UNIVAC 1818 18 20 32 IBM LVDC 26 2.0 32

Original page 26

SCRATCH PAD Par/ Instr. Time Time S peed I Index Ser. Set μ sec) (μ sec) U sec)Re isters P 87 6 12 33-45 15.4 1H 25() words P 27 12 42-54 18.3 None None P 31 12 90 18.9 28 M None ARITM iETIC F; EATURES ADDRE Add Mul F ,ated - 4k words P 70 2.5- 15-24 6.0 .4 H 3.1 2 k words P 64 6.0 18-30 7.0 4 H None P 64 2.0 12.0 4.0 6 H Opt. P 92 4.0 24 5.2 3 H 8H Opt. P 64 2 9-15 N1 1 8 H P 51(b)' NIA 8 M None 8.5(b) 12 (b) 31(e)I 5.0(e) 42 (e) 1.66(r) 8.7 (r) 2.6 None P 78 16 H 5.0 (m) 12.0 (m) None P 63 6.3 19.8-34 512 M 7.8 i 8 H and None P 63 3.6 10-17 512 M 4.6 None P 63 1.8 8.1 2.3 3 H and 512 M None P 63 6.3 12.6-21.5 1024 M 7.0 7 H and None P 63 3.6 6.3-9.9 4.0 1024M 7 H and None P 63 1.8 4.5- 8.1 2.4 it 1024 M None P 39 8.0 72 11.1 7 M Opt. P 27 10 70 17.0 1 H 1 k words Opt. 32 k words None P 47 8 64 14.5 7 M P 62 2 18 3.9 7 M P 32 4 -6 24.5 N/A 3 H 1 1 1 S 18 82 328 190.1 None I,--

Original page 27

1 3SING CAPABILITIES INPUT/OUTPUT PHYSICAL (12 k mr,—VIORY) Page Chan. No. Speed Inter- Weight Vol. Power Indirect Reference (parallel) 10 WPS ru is lbs cu. ft. watts Size No Direct • - 1 No Relative 128 or 1 to Bar 512 Yes Direct to ` -- 2 32 k Yes Direct - 3 Yes Direct -- 2 Yes Direct -- 4 Yes Direct to 1 k 1 k 1 Relative to Bar Yes Direct -- 2 No Relative - 2 to Bar No Relative -- 3 to Bar Yes Direct to 32 1 -- 8 Relative to Bar >32 Yes -- 8 Yes -- 8 Yes -- 8 Yes -- 8 Yes 8 Relative Yes 4 k 1 to Bar Relative No 4 k 1 to Bar Relative 256 2 No to Bar Direct to 32 -- g No Relative to Bar >32 No Relative 512 1 to Bar 13.8 8 47 .65 175 13.8 1 20 .21 62 - 18.3 8 35 .60 125 100 16 39 1.0 155 333 ext. 16 58 .80 190 82 prog. 166 8-24 60 1.21 194 500 1 16 .2 110 i N/A 32 20 ,375 250 165 aux. 80 burst 8' 37 .8 250 16 5 rnuxc - 80 burst 16 52 .84 300 278 mux . 64 .28 100 38 556 burst 64 40 .31 120 64 46 .36 140 64 38 .28 110 64 44 .33 130 64 50 .38 150 250 None 29 .50 140 3 3 1 33 .56 75 '82 2 55 .67 95 120 135 81 87 1.4 2 50 ? None 55 1.2 268 No Direct 256 256 Serial 12 F 78.5 2,2 142 words Bus Relative Bar

Original page 28

RELIA- BILITY I COMPATIBILITY ITBF (hrs) (Manuf. Est. 15.6 k Simulated on IBM 2094 18.0 k Simulated on IBM 7094 or CDC 3600 2.8 k Sim. on CDC 1604 or 3600 4.7 k Sim. on CDC 1604 or 3600 SOFT AVAILABILITY OTHE I WARE S, A, C, U Flight tested Rt. clock; S Flight tested S, A, U, D Used in Phoenix Opt. ESA missile S,A,U Flight tested Rt. clock; 4.7 k Sim. on CDC 1604, 3600 S, A, U Prototype 10k Sim. on Honeywell 800 15k Sim. IBM 7094 6.4 k Sim. IBM 7094 Direct on 360-40 up 3.0 k Direct 1800 or Sim.360 5.0 k Direct IBM 360-40 up >2.3 k Sim. IBM 7094 >2.3 k >2.3 k >2.1 k >2.1 k >2.1 k 8.5 k None 20.0 k Sim. IBM 7094 G.E. 635 10.0 k Sim. UNIVAC 1230, I 1206, 490 4.5 k (Direct UNIVAC 1230 1.5 k None 25.0 k . IBAI 7090-94 Rt. clock; S, A Qualification testing Character S, A,D, L Prototype eval. S,.A, C, D, Developmental Flt. pt. h U, L banks S,A C,U Hardware tested Opt. inst. Developmental S, A, C Alterable early 1967 S, A, D,U,L Developmental Multiproc None Prototype tested. S,A,D,L Used in LEM S,-A, L Used for Titan III Rt. clock; evidance S, A, D,U,L Equip, in develop- Rt. clock; ment None New. avail.: 6/67 j I Rt. clock I IA Used in Saturn Separate vehicle processi

Original page 29

ESA; look ahead ESA; look ahead or word addressing '• irdware; ind. mem. set nst. set s sing capability Under i sy f^ t; (( Ri 3 is LEGEND Under ARITHMETIC ADDRESSING and look ahead FEATURES CAPABILITIES (b) 360 Inst. set H = Hardware implement (c) 1800 Inst. set M = Memory implement (e) Add from register P = Parallel (m) Add from memory S = Serial -.. N/A Data not available Bar = Base address register Under SOFTWARE Under OTHER FEATURES- S = Simulator ESA = Ext. specified A = Assembler address t C = Compiler ESI = Ext. specified index D = Diagnostic ESI L = Library U = Utility ESI; ESA ••mux